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(R)
SP3508
Evaluation Board Manual
FEATURES
Easy Evaluation of SP3508 Multi-Protocol Transceiver Eight (8) Drivers and Eight (8) Receivers Current Mode V.35 Drivers Internal Line or Digital Loopback Internal Transceiver Termination Resistors for V.11 and V.35 Termination Network Disable Option Fast 20Mbps Differential Transmission Rates Adheres to CTR1/CTR2 Compliancy Requirements Interface modes:
RS-232(V.28) X.21(V.11) RS-449/V.36(V.10&V.11) EIA-530(V.10&V.11) EIA-530A(V.10&V.11) V.35(V.35&V.28)
DESCRIPTION The SP3508 Evaluation Board is designed to analyze the SP3508 multi-protocol transceivers. The evaluation board provides access points to all of the driver and receiver I/O pins so that the user can measure electrical characteristics and waveforms of each signal. The SP3508 Evaluation Board also includes a DB-25 serial port connector which is configured to a EIA-530 pinout. This allows easy connections to other DTE or DCE systems as well as network analyzers. The evaluation board also has a set of jumpers to allow the user to select the mode of operation and test the data latch feature. Furthermore, the SP3508 Evaluation Board provides the means to test both local and remote driver/receiver Loopback as well as evaluate the SP3508 in a DCE or DTE configuration. This Manual is split into sections to give the user the information necessary to perform a thorough evaluation of the SP3508. The Board Schematic and Layout section describes the I/O pins, the jumpers and the other components used on the evaluation board. The board schematic, layout diagram and DB-25 connector are also covered in the Board Schematic and Layout section. The Using the SP3508 Evaluation Board section details the configuration of the SP3508 evaluation board for parametric testing.
Rev. 8/28/03
SP3508 Evaluation Board Manual
(c) Copyright 2003 Sipex Corporation
1
NOTES 1) Avoid parrallel traces on receiver inputs
Figure 1. SP3508 Schematic Jumper
Figure 1
2) Add Test Point for VCC and GND for attachment of a power supply. 3) Scope probe jack is Berg part # 33JR135-1 4) VDD (pin 76) and VSS1 (Pin 68) are to be routed as directly as possible to CVdd and CVss1 respectively. 0 26 048 09 88 999 12 57 4 15 0 48 1 24 5 77 8 88
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Jumper Jumper Config
78 73 66 48 23
VCC
C7 1uF
CC
V Part Reference
C3C3+ C1C2+ C1+ C2VSS2 SD(a)
97 sda 27 VSS 69 C2ST_B ST_A TT_B TT_A SD_B SD_A 72 C2+ 24 C1+1 26 C1-1 2
GND
92 96 28
68
VSS1
C3 1uF 1+ + CVss2 1uF
GNDTP CVdd 1uF Vdd
VDD 76
CVss1 1uF + + C1 1uF + C1+ 74
VDD TxD SD(b)
99 sdb C1- 70
C2 1uF 12 Vss_2 2 P1-2 P1-14 14 24 11 15 12 4 19 20 23
1 5) C1, C2, C3, CVdd, CVss1 and CVss2 footprint are size 1812 and are to be as close the the socket pins as 2 possible. 3 6) C7 is footprint 2220 and is to be placed where the power supply is attached to the board. Signal to be 7) Test points are MilMax part # 0300-1-15-01-4727100 0.040" round post. accessed by DB25 8) JP1, JP2 ,JP3, JP4 and JP20 - JP41 are 3 pin 0.100" headers with 0.025" square post STa TxCa 9) JP5, JP9, JP50 and JP51 are 2 pin 0.100" headers with 0.25" square post STb 10) P1 is 25 pin male right angle D-SUB connector TxCb RRTa 11) SP3508 is a 100 pin LQFP RRCa 12) R1 and R2 are 1/8 watt 50 ohm axial lead resistor RRTb 13) U4 is Pomona Type 4788 BNC right angle female PC mount RRCb
JP1 JP1 JP2 JP2 JP3 JP3 JP4 JP4
TP31 TP32
1-2 2-3 1-2 2-3 1-2 2-3 1-2 2-3
TP21 TxD
TXD 31
TP22 TxCE
TXCE 32
TxCE TT(b)
95 ttb sta stb rsa rsb tra trb rrca rrcb 89 91 81 83 85 87 79 77
TT(a)
93 tta
P1-24 P1-11 P1-15 P1-12 P1-4 P1-19
TP33 TP34
TP23 ST
ST 33
ST(a) ST ST(b) RS(a)
RTS 34
JP50 21 JP2 2 13 TP24 RTS
RTS RS(b) TR(a)
ttl
JP1 2 13
TP35 TP36
GND
AGND
TP37 TP38
V TP25 DTR
DTR 35
CC
AV
DTR TR(b) RRC(a) RRC(b) RL
67 rla 21
CC
JP51 12 TTL TP26
DCE_DCE 36
P1-20 P1-23
TP39 TP40
DCD_DCE
TP41 TP42
DCE_DCE TP27 RL
RL 37
1 P1-21 RL_A R R C _ B T R _ B T R _ A R R C _ A R S _ B R S _ A JP5 TP28
LL 38 18 lla
RL(a)
R1 50 P1-1
TP43 TP44
BNC LL
LL
65
2
LL(a)
TP45 TP46
RT_B RT_A RD_B RD_A
1 R2 50
RD(a)
50 rda rdb rta rtb txca txcb csa csb dma dmb rrta rrtb 49 52 51 55 53 57 56 59 58 62 61 RXD 39
P1-18 LL_A
RxD RD(b) RT(a)
3 16 17 9
P1-3 P1-16 P1-17 P1-9
TP47 TP48
JP31
JP29
JP27
JP28
JP30
JP32
JP33
JP26
JP34
JP35
JP36
JP37
JP38
JP39
JP40
JP41
SP3508 Evaluation Board Manual
RXC 40 60 GNDV10
2
RxC RT(b) TxC(a)
TXC 41
TP49 TP50
JP9
TxC TxC(b) CS(a)
CTS 42
GND CTS
CTS CS(b) DM(a)
DSR 43
JP52 Jumper 1 23
TP51 TP52
VCC
4 AC INPUT DSR
DSR DM(b) RRT(a)
DCD_DTE 44
5 13 6 22 JP3 2 13 IC_IN 8 10 JP4 2 13
P1-5 P1-13 P1-6 P1-22 P1-8 P1-10
TP53 TP54
Description
Jumper Configuration DCD_DTE
DCD_DTE RRT(b) IC
63 ic
TP55 TP56
Input to GND
1-2
Input toVCC RI
RI 45
2-3
TP57 TP58
Input frin external source
RI
2-4
V TM
TM_OUT 46
CC
TM
TM(a)
64 TM_IN
R R T _ B
R R T _ A
D M _ B
D M _ A
C S _ B
C S _ A
25
P1-25 GND
Jumper VCC 123 Signal VCC T M _ a
DECODER MODE SHUTDOWN V.35 D0 1 0 D1 1 0 D2 1 1
Signal Term_off Jumper JP20 JP21 GND 1-2 1-2 VCC 2-3 2-3
JP20 123 LATCH TERM_OFF
latch termoff 21 22
JP21 12 3
/D_LATCH TERM_OFF
/RDEN /RTEN /TxCEN /CSEN /DMEN /RRTEN /ICEN TMEN
10 11 12 13 14 15 16 17 rden rten txcen csen dmen rrten icen tmen
D1 D0
D0 D2 18 D0 D1 19 D1 20 D2 LOOPBACK 30 /LOOPBACK
3 3 3 33 3 33 22222222 1 11 1 11 1 1
JP22 V
CC
/D_Latch D0 D1 D2
JP22 JP23 JP24
1-2 1-2 1-2
2-3 2-3 2-3
123
JP23 D2 LOOPBACK
JP24
1 23
12 3
JP25
SDE TTE STE RSE TRE RRCE RLEN /LLEN
2 3 4 5 6 7 8 9
sden tten sten rsen tren rrcen rlen llen
12 3
V
EIA-530
CC
0 RS-232 EIA-530A 0 1
1 1 0
0 1 0
/Loopback TMEN /ICEN /RRTEN /DMEN /CSEN
JP25 JP26 JP27 JP28 JP29 JP30
1-2 1-2 1-2 1-2 1-2 1-2
2-3 2-3 2-3 2-3 2-3 2-3
3 3 3 33 3 33 22222222 1 11 1 11 1 1
RS-449 X.21
1 1
0 1
1 0
/TxCEN /RTEN /RDEN /LLEN RLEN RRCEN TREN RSEN STEN TTEN SDEN
JP31 JP32 JP33 JP34 JP35 JP36 JP37 JP38 JP39 JP40 JP41
1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2
2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3
(c) Copyright 2003 Sipex Corporation
SP508 EVALUATION BOARD BOARD LAYOUT 1. The SP3508 Evaluation Board has been designed to easily and conveniently provide access to all inputs and outputs under test. 2. Figure 1 is a schematic of the evaluation board. The schematic shows the location of the driver and receiver access points as well as the Jumpers, VCC, GND and the DB-25 Connector. 3. Figure 3 to Figure 6 shows the layout of the SP3508 Evaluation Board. 4. I/O Pinouts The SP3508 Evaluation Board has been designed to easily and conveniently provide access to all inputs and outputs to the device under test. Each Driver has probe points for the inputs and outputs. Each Receiver has probe points for the inputs and outputs. 5. At the left of the board is a set of jumpers. Each driver and receiver has its own individual enable pin. This set of jumpers controls the enabling and disabling of each driver of receiver. Another set of jumpers is to configure the 3 bit decoder, to enable/ disable loopback, to enable/disable latch and to enable/disable term_off functions. In addition, JP1 - JP4 allow the user to choose which signals the user can access through the DB-25 connector. JP5 allows the user to set the driver input to GND, VCC or external source. 6. Also located on the SP3508 evaluation board are six 1uf charge pump capacitors, a 1F bypass capacitor for VCC and two 50 termination resistors. 7. 1 Pomona BNC female connector is mounted on the board to provide input signal for evaluation. 8. Figure 2 shows a RS-232 & EIA530 DB25 Connector. 9. Table 1 shows the pinout of the DB-25 connector used to connect to a communication analyzer such as the TTC Firebird 6000.
1
13
14
25
Figure 2. RS-232 & EIA530 Connector (ISO 2110), DTE Connector DB-25 Male, DCE Connector DB-25 Female
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(c) Copyright 2003 Sipex Corporation
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Transmitter Outputs
Transmitter and Receiver Enable Pins
Receiver Inputs
Receiver Outputs
Transmitter Inputs
Note: All six charge pump caps are located next to the DUT. Control pins (D0,D1, D2), / LOOPBACK, / D_LATCH, and TERMOFF are also included.
Figure 3. SP3508 Evaluation Board Layout
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(c) Copyright 2003 Sipex Corporation
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Figure 4. SP3508 Evaluation Board Ground Plane
Figure 5. SP3508 Evaluation Board VCC Plane
Rev. 8/28/03 SP3508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation
5
Figure 6. SP3508 Evaluation Board Layout Bottom Layer
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TABLE 1.
EIA-232
Signal Name source Mnemonic Pin
EIA-530
Mnemonic Pin
EIA-449
Mnemonic Pin
V.35
Mnemonic Pin
X.21
Mnemonic Pin
Shield Transmitted data
-- DTE
-- BA
1 2
-- BA(A) BA(B)
1 2 14 3 16 4 19 5 13 6 22 20 23 7 8 10 15 12 17 9 18 21 -- 24 11 25
-- SD(A) SD(B) RD(A) RD(B) RS(A) RS(B) CS(A) CS(B) DM(A) DM(B) TR(A) TR(B) SG RR(A) RR(B) ST(A) ST(B) RT(A) RT(B) LL RL -- TT(A) TT(B) TM
1 4 22 6 24 7 25 9 27 11 29 12 30 19 13 31 5 23 8 26 10 14 -- 17 35 18
-- 103 103 104 104 105
A P S R T C
-- Circuit T(A) Circuit T(B) Circuit R(A) Circuit R(B) Circuit C(A) Circuit C(B)
1 2 9 4 11 3 10 5 12
Received Data
DCE
BB
3
BB(A) BB(B)
Request To Send
DTE
CA
4
CA(A) CA(B)
Clear To Send
DCE
CB
5
CB(A) CB(B)
106
D
Circuit I(A) Circuit I(B)
DCE Ready (DSR) DCE
CC
6
CC(A) CC(B)
107
E
DTE Ready (DTR)
DTE
CD
20
CD(A) CD(B)
108
H*
Signal Ground Recv. Line Sig. Det. (DCD) Trans. Sig. Elemt. Timing Recv. Sig. Elemt. Timing Local Loopback Remote Loopback Ring Indicator Trans. Sig. Elemt. Timing Test Mode
-- DCE
AB CF
7 8
AB CF(A) CF(B)
102 109
B F
Circuit G
8
DCE
DB
15
DB(A) DB(B)
114 114 115 115 141 140 125 113 113 142
Y AA V X L* N* J* U* W* NN*
Circuit S(A) Circuit S(B) Circuit B(A)** Circuit B(B)**
6 13 7 14
DTE
RL
17
DD(A) DD(B)
DCE DTE DCE DTE
DD LL CE DA
18 21 22 24
LL RL -- DA(A) DA(B)
Circuit X(A)** Circuit X(B)**
7 14
DCE
TM
25
TM
* Optional signals ** Only one of the two x.21 signals, Circuit B or X, can be implemented and active at one time.
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SP3508 Evaluation Board Manual
(c) Copyright 2003 Sipex Corporation
7
USING THE EVALUATION BOARD Recommended Equipment * Oscilloscope * Digital multimeter * Signal Generator capable of >40MHz * Communications Analyzer (such as Firebird 6000) Parametric Evaluation Located on the board are two pins identified as VCC and SIGNAL GND. Connect VCC to a +3.3V DC supply. If possible limit the supply current to 0.5 to 1.0 Amps. Be sure to have power off when connecting the supply to the board. SP3508 Decoder The SP3508 uses a 3 bit decoder to designate the protocol selected. There is also a decoder latch pin available. Table 2 and Table 3 show the decoder modes for the driver and receiver. Upon power up the latch pin needs to be in a transparent state (logic low or floating) or the SP3508 will be in an unknown state. Note that D0, D1, and D2 set as logic high will put the device shutdown overriding all individual enable/ disable lines and the drivers outputs and receiver inputs will tri-state. In shutdown mode the termination resistors also disconnect. Driver Evaluation Each driver has an internal pull-up; therefore, it is in a defined state when the input is open. Connect a system clock or a signal generator with a TTL-level output and the appropriate frequency within the acceptable range of the driver to the input BNC connector. Set the jumper to the desired driver input to be evaluated. There is an individual enable line for each driver that can be used to tri-state the driver. Each enable line has an internal pull up or pull down to insure the driver is enabled if the enable pin is not connected or floating. Set the appropriate jumper to enable the driver under test. Once the power is on and the driver input receives a signal, the driver outputs can be analyzed with an oscilloscope or a digital multimeter. Mode selection can be performed at any time by changing the jumper settings for the 3 bit decoder (D0-D2). The appropriate termination for the driver under test can be added to driver output and tied to the ground bus. Receiver Evaluation The SP3508 receivers have internal termination appropriate for V.35 and RS-422 modes (refer to the SP3508 datasheet for more detail on the receiver termination). This is activated when the receiver is set to act as a V.11 receiver (see Table 3) and the TERM_OFF pin is logic "0". Each receiver has a fail-safe feature that outputs a logic "1" when the receiver is open, terminated but open, or shorted together. There is an individual enable line for each receiver that can be used to tri-state the driver. Each enable line has an internal pull up or pull down to insure the receiver is enabled if the enable pin is not connected or floating. Set the appropriate jumper to enable the receiver under test. The mode selection can be performed at any time after power up by changing the state of the 3 bit decoder (D0D2). To evaluate the receiver the appropriate input signal needs to be applied. This can be accomplished by providing a signal from an external source or use the SP3508 driver output and jumper it to the receiver input. For single ended receivers, tie the active driver output to the active receiver input. For differential drivers, tie the "A" driver output to the "A" receiver input and the "B" driver output to the "B" receiver input. Using the TTL signal on the driver input will allow the user to analyze receiver levels and timing characteristics.
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SP3508 Evaluation Board Manual
(c) Copyright 2003 Sipex Corporation
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USING THE EVALUATION BOARD: Continued Driver/Receiver Remote Loopback The following example uses the ST driver looped back into the TxC receiver. Use the 3 bit decoder to configure the SP3508 for the desired protocol. Connect a jumper cable between the ST(a) pin and the TxC(a) pin. If your mode select is set for a differential driver/receiver, then also connect a jumper cable between the ST(b) pin and the TxC(b) pin. The next step is to connect a signal generator to the ST input pin through BNC input connector. The signal generator output must be a TTL-level output at a frequency within the acceptable range of the driver mode under test. Be sure that the jumper settings of STEN signal and TxCEN signal are set to enable the ST driver and TxC receiver. The driver outputs are now connected back to the receiver inputs so that the driver input to receiver output can be examined. This configuration is similar for all other drivers. Driver/Receiver Local Loopback The SP3508 has the ability to provide an internal loopback. This feature is invoked by a logic "0" on the /LOOPBACK pin. The driver input and receiver output characteristics adhere to the appropriate specifications outlined in the datasheet under loopback conditions. The /LOOPBACK pin has an internal pull-up resistor so that the SP3508 defaults to normal operation during powerup or if the pin is left floating. DCE DTE selectable configuration * Configure the decoder for the desired mode. * The SP3508 evaluation board has jumper setup to allow for the evaluation of a selectable DCE DTE configuration. * Set the STEN and RRCEN to Logic "0". This will disable the ST and RRC driver outputs. (Refer to the Jumper Setting Guide in the next section) * Set the /TxCEN and /RRTEN to Logic "1". This will disable the TxC and RRT receiver inputs. (Refer to the Jumper Setting Guide in the next section) * Use an external wire to tie the ST driver outputs to the TxC Receiver inputs. * Use an external wire to tie the RRC driver outputs to the RRT receiver inputs. * To enable a DTE configuration, set the STEN and RRCEN to Logic "1". Be sure the TxC and RRT receivers are disabled by setting the /TxCEN and /RRTEN to Logic "1". (Refer to the Jumper Setting Guide in the next section) * To enable a DCE configuration, set the / TxCEN and /RRTEN to Logic "0". Be sure to disable the ST and RRC driver outputs by setting the STEN and RRCEN to Logic "0". (Refer to the Jumper Setting Guide in the next section) System Level Evaluation * Use DB-25 Connector if the evaluation board is configured as a DTE for EIA-530 pinout. In order to connect to other DCE equipment or network analyzers ( i.e. the TTC Firebird 6000A), the RxC receiver output must be looped back to the TxCE driver input. The RxD output can also be looped back to the TxD input. * If connecting the evaluation board to a microcontroller such as the Motorola MC68360, jumper wires of the driver inputs and receiver outputs must connect to the uC's appropriate pins.
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(c) Copyright 2003 Sipex Corporation
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TABLE 2
Driver Output Pin MODE (D0,D1,D2) T1OUT(a) T1OUT(b) T2OUT(a) T2OUT(b) T3OUT(a) T3OUT(b) T4OUT(a) T4OUT(b) T5OUT(a) T5OUT(b) T6OUT(a) T6OUT(b) T7OUT(a) T8OUT(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 EIA-530A RS-449 X.21 Mode (V.28) Mode Mode (v.36) Mode (v.11) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z TxD(a) TxD(b) TxCE(a) TxCE(b) TxC_DCE(a) TxC_DCE(b) RTS(a) RTS(b) DTR(a) DTR(b) DCD_DCE(a) DCD_DCE(b) RL LL Suggested Signal
TABLE 3
Receiver Input Pin MODE (D0,D1,D2) R1IN(a) R1IN(b) R2IN(a) R2IN(b) R3IN(a) R3IN(b) R4IN(a) R4IN(b) R5IN(a) R5IN(b) R6IN(a) R6IN(b) R7IN(a) R8IN(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 EIA-530A RS-449 X.21 Mode (V.28) Mode mode (v.36) Mode (v.11) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z RxD(a) RxD(b) RxC(a) RxC(b) TxC_DTE(a) TxC_DTE(b) CTS(a) CTS(b) DSR(a) DSR(b) DCD_DTE(a) DCD_DTE(b) RI TM Suggested Signal
JUMPER SETTING GUIDE JP52 allows the user to set the driver input to GND, VCC or external source. TABLE 4. JP52 JUMPER SETTING
1
2 4
3
Description
Input to GND Input to VCC Input from External Source
Jumper Configuration
1-2 2-3 2-4
Figure 7. JP52 Jumper Configuration.
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(c) Copyright 2003 Sipex Corporation
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Figure 8 shows 3-pin jumper configuration and Table 5 describes the fuctionalities of each jumper setting configuration.
1
2
3
Figure 8. 3-Pin Jumper Configuration
TABLE 5. SP3508 LOGIC JUMPER SETTING
Switch D0 D1 D2 LOOPBACK TERM_OFF D_LATCH SDEN TTEN STEN RSEN TREN RRCEN RLEN /LLEN /RDEN /RTEN /TXCEN /CSEN /DMEN /RRTEN /ICEN TMEN Jumper JP22 JP23 JP24 JP25 JP20 JP21 JP41 JP40 JP39 JP38 JP37 JP36 JP35 JP34 JP33 JP32 JP31 JP30 JP29 JP28 JP27 JP26 LOGIC 1 VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) LOGIC 2 GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) DECODER DECODER DECODER Logic 0 indicates SP508 is in LOOPBACK mode Logic 1 internal termination is disables Logic 0 Latch is disabled Logic 1 TXD driver is enabled Logic 1 TXCE driver is enabled Logic 1 ST driver is enabled Logic 1 RTS driver is enabled Logic 1 DTR driver is enabled Logic 1 DCD_DCE driver is enabled Logic 1 SD driver is enabled Logic 0 LL driver is enabled Logic 0 RXD receiver is enabled Logic 0 RXT receiver is enabled Logic 0 TXC receiver is enabled Logic 0 CTS receiver is enabled Logic 0 DSR receiver is enabled Logic 0 DCD_DTE receiver is enabled Logic 0 RI receiver is enabled Logic 1 TM receiver is enabled
JP1 - JP4 are set of jumpers that the user can select which signals to be accessed by DB25. Figure 9 shows 3-pin jumper configuration and Table 5 describes the signal to be accessed by DB25 per its configuration. TABLE 6. SP3508 JUMPER SETTINGS
1 2 3
Signal to be accessed by DB25
STa TxCa STb TxCb RRTa RRCa RRTb RRCb
SP3508 Evaluation Board Manual
Jumper
Jumper Configuration
1-2 2-3 1-2 2-3 1-2 2-3 1-2 2-3
Figure 9. 3-Pin Jumper Configuration
JP1 JP1 JP2 JP2 JP3 JP3 JP4 JP4
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SP3508 Pin Designation
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Pin Name GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN RDEN RTEN TxCEN CSEN DMEN RRTEN ICEN TMEN D0 D1 D2 D_LATCH VCC C3P GND C3N VSS2 AGND AVCC TxD TxCE ST RTS DTR DCD_DCE RL LL RxD RxC TxC CTS DSR DCD_DTE RI TM GND VCC RD(B) RD(A)
Description Signal Ground TxD Driver Enable Input TxCE Driver Enable Input ST Driver Enable Input RTS Driver Enable Input DTR Driver Enable Input DCD Driver Enable Input RL Driver Enable Input LL Driver Enable Input RxD Receiver Enable Input RxT Receiver Enable Input TxC Receiver Enable Input CTS Receiver Enable Input DSR Receiver Enable Input DCDDTE Receiver Enable Input RI Receiver Enable Input TM Receiver Enable Input Mode Select Input Mode Select Input Mode Select Input Decoder Latch Input Power Supply Input Charge Pump Capacitor Signal Ground Charge Pump Capacitor Minus VCC Signal Ground Power Supply Input TxD Driver TTL Input TxCE Driver TTL Input ST Driver TTL Input RTS Driver TTL Input DTR Driver TTL Input DCDDCE Driver TTL Input RL Driver TTL Input LL Driver TTL Input RxD Receiver TTL Output RxC Receiver TTLOutput TxC Receiver TTL Output CTS Receiver TTL Output DSR Receiver TTL Output DCDDTE Receiver TTL Output TI Receiver TTL Output TM Receiver TTL Output Signal Ground Power Supply Input RXD Non-Inverting Input RXD Inverting Input
Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
SP3508 Evaluation Board Manual
Pin Name RT(B) RT(A) TxC(B) GND TxC(A) CS(B) CS(A) DM(B) DM(A) GNDV10 RRT(B) RRT(A) IC TM(A) LL(A) VCC RL(A) VSS1 C2N C1N GND C2P VCC C1P GND VDD RRC(B) VCC RRC(A) GND RS(A) VCC RS(B) GND TR(A) VCC TR(B) GND ST(A) VCC ST(B) GND TT(A) VCC TT(B) GND SD(A) VCC SD(B) VCC
Description RxT Non-Inverting Input RxT Non-Inverting Input TxC Non-Inverting Input Signal Ground TxC Inverting Input CTS Non-Inverting Input CTS Inverting Input DSR Non-Inverting Input DSR Inverting Input V.10 Rx Reference Node DCDDTE Non-Inverting Input DCDDTE Non-Inverting Input RI Receiver Input TM Receiver Input LL Driver Output Power Supply Input RL Driver Output -2xVCC Charge Pump Output Charge Pump Capacitor Charge Pump Capacitor Signal Ground Charge Pump Capacitor Power Supply Input Charge Pump Capacitor Signal Ground 2xVCC Charge Pump Output DCDDCE Non-Inverting Output Power Supply Input DCDDCE Inverting Output Signal Ground RTS Inverting Output Power Supply Input RTS Non-Inverting Output Signal Ground DTR Inverting Output Power Supply Input DTR Non-Inverting Output Signal Ground ST Inverting Output Power Supply Input ST Non-Inverting Output Signal Ground TxCE Inverting Output Power Supply Input TxCE Inverting Output Signal Ground TxD Inverting Output Power Supply Input TxD Non-Inverting Output Power Supply Input
(c) Copyright 2003 Sipex Corporation
TERM_OFF Termination Disable Input
LOOPBACK Loopback Mode Enable Input
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ORDERING INFORMATION
Model TEMPERATURE Package SP3508CF ........................................................ 0C TO +70C ..................................... 100-pin JEDEC LQFP SP508CEB ....................................................... 0C TO +70C ................................. SP508 Evaluation Board
Corporation
ANALOG EXCELLENCE
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Rev. 8/28/03 SP3508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation
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